The present invention relates to a method and apparatus for creating imaging recipe used to acquire images at any position on a sample with a critical-dimension scanning electron microscope (CD-SEM) or the like. The imaging recipe defines not only coordinates of imaging points of addressing point and evaluation point (end measuring point), but also the image templates or imaging conditions (or the like) that are associated with the above coordinates. The invention is also concerned with an apparatus (SEM apparatus) for evaluating shapes of patterns formed on semiconductor wafers.
Traditionally, CD-SEMs and the like are most commonly used to inspect the workmanship of the highly accurate wiring patterns formed on semiconductor wafers.In SEM apparatuses such as the CD-SEMS, dimensionally critical points on the semiconductor patterns to be inspected are observed as measuring points through the SEM, then various dimensional data on the patterns, such as wiring widths, are measured from the images acquired during the observation process, and the dimensional data is monitored to detect changes in process parameters.
To perform these inspections, it is necessary to create the imaging recipe that defines the coordinates of imaging points, imaging conditions, image templates of each imaging point, and other data.
Japanese Patent Laid-Open Nos. 2002-328015 and 2000-236007 disclose examples of a known technique for creating imaging recipe used with such a SEM apparatus.
Japanese Patent Laid-Open No. 2002-328015 describes a semiconductor inspection system constituted by two sub-systems. One is a navigation system that stores CAD data and other design information on a semiconductor wafer and uses the stored design information to set the imaging/inspection conditions including the regions of the semiconductor wafer that are to be inspected. The other is a scanning electron microscopic system that acquires images of the semiconductor wafer in accordance with the set imaging/inspection conditions and is executed inspection of patterns. According to Japanese Patent Laid-Open No. 2002-328015, this semiconductor inspection system also has a function that detects the position of an addressing point (AP) from the CAD data and registers the CAD data of this detected position as a template. In addition, this system has a function that acquires a SEM image associated with the AP, then matches between the acquired SEM image and the registered CAD template at the AP, and after re-registering as another template the SEM image associated with the position of the CAD template, uses the re-registered SEM template subsequently.
Also, Japanese Patent Laid-Open No. 2000-236007 describes a method of creating sequence files for automatic detection with a scanning electron microscope. This file-creating method includes five process steps: acquiring design data from CAD data; acquiring pattern data of any region from the design data; extracting pattern contour edge data on the basis of the pattern data; specifying from the pattern outline edge data the sections to be measured; and setting template edge data from the pattern outline edge data associated with the specified sections.
For the semiconductor inspection system described in Japanese Patent Laid-Open No. 2002-328015, however, a linear image created from the CAD data (for example, an image on which only the boundary of a mask for forming pattern on a resist is represented as edges) is used to determine imaging points manually or automatically. Therefore, there has been the problem that appropriate imaging points cannot be selected because of a significant difference in visual or apparent position between the above linear image and an actual SEM image.
Also, using the method based on optical simulation or resist shape simulation, described in Japanese Patent Laid-Open No. 2000-236007, requires setting resist information (atomic composition ratio, film thickness, negative/positive attribute, light transmittance, light absorption energy, and others), the optical constants (wavelength, numerical aperture, s, the kind of mask, and others) of the light exposure apparatus used, developing agent information (composition, developing rate coefficient, developing time, and others), and other various simulation parameters. In addition, these simulation parameters are not easy to set. Furthermore, the simulation parameters could include those which vary according to the particular position on the wafer surface or a particular time.